Next generation FPGA application on the ATLAS calorimeter trigger board dedicated to jet identification
To cope with the enhanced luminosity delivered by the Large Hadron Collider (LHC) in 2021, the ATLAS experiment has planned a major upgrade. As part of this, the first level trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature EXtractors (FEXs), which each use different physics objects for the trigger selection. The three FEXs are: the electromagnetic FEX (eFEX), the jet FEX (jFEX) and the global FEX (gFEX) that identify electron/photon and tau signatures, (large area) jets and global variables, respectively. The main difference between the jFEX and the gFEX is the granularity of the data received from the calorimeters. This presentation describes the general upgrade concept of the first level calorimeter trigger and focusses then on the design and tests of the jFEX prototype. Up to 2 Tb/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within a few hundred nanoseconds latency budget. This requires the use of large Field Programmable Gate Arrays (FPGAs) with the largest number of Multi Gigabit Transceivers (MGTs) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signal board. MEGTRON6 was chosen as the material for the 24 layers jFEX board stack-up because of its property of low transmission loss with high frequency signals (GHz range) and to further preserve the signal integrity. Special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. The first results from numerous tests on the prototype are reported with special emphasis on high- speed signal quality.