27 February 2017 to 3 March 2017
Budker Institute of Nuclear Physics
Asia/Novosibirsk timezone

Monitoring Single Event Upsets in SRAM-based FPGAs at the SuperKEKB Interaction Point

3 Mar 2017, 10:20
20m
Contributed Oral Electronics, Trigger and Data Acquisition Electronics, Trigger and Data Acquisition

Speaker

Dr Raffaele Giordano (University of Naples and INFN)

Description

Static RAM-based Field Programmable Gate Arrays (SRAM-based FPGAs) [1, 2] are widely adopted in Trigger and Data Acquisition (TDAQ) systems of High-Energy Physics (HEP) experiments for implementing fast logic due to their re-configurability, large real-time processing capabilities and embedded high-speed serial IOs. However, these devices are sensitive to radiation effects such as single event upsets (SEUs) or multiple bit upsets (MBUs) in the configuration memory, which may alter the functionality of the implemented circuit. Therefore, they are normally employed only in off-detector regions, where no radiation is present. Special families of SRAM-based FPGAs (e.g. the Xilinx Virtex-5QV) have been designed for applications in radiation environments, but their excessive cost (few 10k USD), with respect to their standard counterpart ($\sim$ 500 USD), usually forbids their usage in many applications, including HEP. Therefore, there is a strong interest in finding solutions for enabling the usage of standard SRAM-based FPGAs also on-detector. Methods based on modular redundancy and periodic refresh of the configuration, i.e. configuration scrubbing, are used in order to mitigate single event effects, which become more significant as the technological scaling proceeds towards smaller feature sizes. In fact, latest devices also include dedicated circuitry implementing error correcting codes for mitigating configuration errors. The expected bit configuration upset rate is valuable information for choosing which protection strategy, or which mixture of strategies, to adopt. Typically, test campaigns are carried out at dedicated irradiation facilities by means of heavy ions, proton and neutron beams [3,4,5] and they permit to determine the particle to bit error cross section. However, a reliable prediction of the upset rate, and of radiation effects in general, requires the knowledge of the cross section as function of the particle species and their spectra and it depends on a detailed knowledge of the radiation fluxes. Often such information is not available with sufficient precision, and when possible an in situ (or in flight for space applications) measurement of the upset rate is highly recommended. For instance, experiments at the Large Hadron Collider have been monitoring SEUs in readout control FPGAs [6], experiments in space have been launched in order to measure single event effects rates and compare them to predictions based on cross sections [7]. Furthermore, over the last decade, FPGA vendors have been carrying out experiments aimed at measuring SEUs induced by atmospheric neutrons in their devices [8]. In February 2016, the SuperKEKB [9] $e^+e^-$ high-luminosity ($8\cdot10^{35} cm^{-2} s^{-1}$) collider of the KEK laboratory (Tsukuba, Japan) started being commissioned. A dedicated commissioning detector, named BEAST2, has been being used to characterize beam backgrounds prior to the Belle2 detector roll into the beams and to provide tuning parameters for Monte Carlo simulations. BEAST2 consists of a fiberglass support structure and several subdetectors mounted onto it, including time projection chambers (TPCs) and He-3 tubes. In this work, we present direct measurements of radiation-induced soft-errors on a SRAM-based FPGA device installed on the BEAST2 frame at a distance of $\sim$ 1 m from the beam interaction point. Our goal is to provide experimental results of the expected FPGA configuration error rate and power consumption variation at Belle2 and at other experiments operating in similar radiation conditions. For this study, we designed a dedicated board hosting a Xilinx Kintex-7 325T device without additional active components, in such a way to be able to decouple FPGA failures from those of other devices. The board receives power and clock from dedicated remote generators installed in a counting room. The configuration and read back are performed via a JTAG connection and they are managed by a dedicated single board computer . During the commissioning of the collider, we periodically read back the FPGA configuration in order to detect errors and we logged the power consumption on the different power domains of the device. Currents for both electron and positron rings spanned a range between 50 and 500 mA, therefore providing data about the FPGA in different radiation conditions. Even if the machine is not providing collisions yet, as the beams are not focused to the interaction point, our results show a rate of 0.02 upsets/day averaged over the whole commissioning time frame. BEAST2 subdetectors provided valuable information about the radiation environment. This work is part of the ROAL SIR project funded by the Italian Ministry of Research (MIUR). References [1] Xilinx Inc., “Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics,” DS893 (v1.7.1) April 4, 2016 [2] Altera Corp., “Stratix 10 Device Overview,” S10-OVERVIEW, 2015.12.04 [3] D. M. Hiemstra and V. Kirischian, "Single Event Upset Characterization of the Kintex-7 Field Programmable Gate Array Using Proton Irradiation," 2014 IEEE Radiation Effects Data Workshop (REDW), Paris, 2014, pp. 1-4. doi: 10.1109/REDW.2014.7004593 [4] M.J. Wirthlin, H. Takai and A. Harding, “Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter ,” in Proc. of Topical Workshop on Electronics for Particle Physics 2013, Perugia, Italy [5] T. Higuchi, M. Nakao and E. Nakano, “Radiation tolerance of readout electronics for Belle II,” in Proc. of Topical Workshop on Electronics for Particle Physics 2011, Vienna, Austria [6] K. Røed, J. Alme, D. Fehlker, C. Lippmann and A. Rehman, “First measurement of single event upsets in the readout control FPGA of the ALICE TPC detector,” in Proc. of Topical Workshop on Electronics for Particle Physics 2011, Vienna, Austria [7] A. Samaras, A. Varotsou, N. Chatry, E. Lorfevre, F. Bezerra and R. Ecoffet, "CARMEN1 and CARMEN2 Experiment: Comparison between In-Flight Measured SEE Rates and Predictions," 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Moscow, 2015, pp. 1-6. doi: 10.1109/RADECS.2015.7365590 [8] Xilinx Inc., “Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits,” WP286 (v2.0) March 22, 2016 [9] I. Adachi, “Status of Belle II and SuperKEKB,” Journal of Instrumentation, Volume 9, July 2014

Summary

In February 2016, the SuperKEKB positron-electron high-luminosity
collider of the KEK laboratory (Tsukuba, Japan) started being commissioned.
A dedicated commissioning detector, named BEAST2, has been used to
characterize beam backgrounds before the Belle2 detector is rolled
into the beams and to provide tuning parameters for Monte Carlo simulations.
BEAST2 consists of a fiberglass support structure and several subdetectors
mounted onto it, including time projection chambers (TPCs) and He-3
tubes. In this work, we present direct measurements of radiation-induced
single event upsets in a SRAM-based FPGA device installed in BEAST2
at a distance of $\sim$ 1 m from the beam interaction point.

Our goal is to provide experimental results of the expected radiation-induced
configuration upset rate and power consumption variation at Belle2
and at other experiments operating in similar radiation conditions.
For this study, we designed a dedicated board hosting a Xilinx Kintex-7
325T FPGA without additional active components, in such a way to be
able to decouple FPGA failures from those of other devices. During
the commissioning of the collider, we periodically read back the FPGA
configuration in order to detect errors and we logged the power consumption
on the different power domains of the device. Currents for both electron
and positron rings spanned a range between 50 and 500 mA, therefore
providing data about the FPGA operation in different radiation conditions.

Primary authors

Prof. Alberto Aloisio (University of Naples "Federico II" and INFN Naples) Dr Raffaele Giordano (University of Naples and INFN) Dr Sabrina Perrella (University of Naples "Federico II" and INFN Naples) Dr Vincenzo Izzo (INFN Naples)

Presentation Materials