from 24 February 2014 to 1 March 2014
Asia/Novosibirsk timezone
Home > Timetable > Session details > Contribution details

Contribution Oral presentation

Trigger, electronics and DAQ

The Belle II Pixel Detector DAQ

Speakers

  • David MUENCHOW

Primary authors

Abstract content

At the future Belle II experiment the inner DEPFET (DEPleted Field Effect Transistor) pixel detector will consist of ~8 million channels. Because of its small distance to the interaction region and the high luminosity in Belle II, for a trigger rate of ~30 kHz with an estimated occupancy of ~3% a data rate of ~22 GB/s is expected. Due to the high data rate a reduction factor higher than 30 is needed to achieve the specifications of the event builder. The main hardware to reduce the data rate is an ATCA based Compute Node (CN) developed in cooperation between IHEP Beijing and University Giessen. Each node has as main component a Xilinx Virtex-5 FX70T and uses the xTCA standard. The CN is equipped with 2x2 GB RAM , GBit Ethernet and 4x6.25 Gb/s optical links. An additional carrier board is able to hold up to four CN and supplies high bandwidth connections between the four CNs and to the ATCA backplane. To fulfill the required data reduction on the CNs Regions of Interest (ROI) are used. This regions are calculated in two independent systems by projecting tracks back to the pixel detector. One is the High Level Trigger (HLT) which uses the data from the outer detectors. The other is the Data Concentrator (DatCon) which calculates based on Silicon Vertex Detector (SVD) data only to get low momentum tracks. With this information only data inside this ROIs will be forwarded to the event builder while data outside of this regions will be discarded. The ROI selection and the buffer managment for the data stored in RAM is implemented in VHDL, as well as a merging system to combine the ROI data from HLT and DatCon. First results of the test beam time in january 2014 at DESY with a prototype detector and full DAQ chain will be presented.