24-28 February 2020
Budker Institute of Nuclear Physics
Asia/Novosibirsk timezone

Current and Future FPGA-TDC Developments at GSI

25 Feb 2020, 16:00
Invited Oral Electronics, Trigger and Data Acquisition Electronics, Trigger and Data Acquisition


Dr Michael Traxler (GSI Helmholtzzentrum für Schwerionenforschung GmbH)


High precision time measurements as well as pulse width encoded charge measurements are a crucial element in particle identification detectors. FPGA based time-to-digital converters have been proven to be very useful devices for this task. The design efforts at GSI lay special emphasis on providing low and lowest cost platforms for TDCs. This is due to the fact that in particle physics, massive amounts of TDCs are used in detector facilities. Therefore, we target absolute low cost devices such as Lattice ECP5, while keeping the timing performance on the already achieved level and still improving many more aspects. Two different second generation architectures are currently under development: Eraser and Eins11!. For Eraser, the target specs are: ~10ps time precision RMS with 48 channels on ECP5, and 64 channels on ECP3. Eins11! can provide 64 channels in the ECP5, but with a lower precision in the order of 100ps. Further features of both architechtures are: - Channels can be combined pairwise under program control in order to increase precision or decrease deadtime - ToT measurements in any channel using a stretcher, or using two channels - Increased resolution by having two edges in the TDL at any time (Wave Union type A) - 40-bit timestamps - Single-cycle encoder with 100% efficiency running at 290MHz - Pipelined trigger operation: up to 16 triggers can be issued before the first one needs to be returned - Freely positionable trigger window relative to trigger signal - Per-channel trigger window comparator for fast read-out (high trigger rate) - On-the-fly elimination of hits that drop out of the trigger window (on each channel) to lower internal data rate - Additional deadtime-free Sampling-TDC on each channel with a sampling rate of 1.16GS/s - Logic Analyzer Memory for all channels, variable sampling rate, maximum trace length 28us - High-performance 32-bit pulse counter on each channel - On-the-fly fine-time calibration using per-channel lookup tables - Protection against overflow conditions and corrupted input signals On ECP3, a preliminary implementation achieved a precision of 11ps mean. The current target platforms are the proven systems TRB3, TRB3sc, DiRICH as well as the new low-cost ECP5 system TRB5sc.

Primary authors

Dr Günter Knittel (GSI Helmholtzzentrum für Schwerionenforschung GmbH) Dr Michael Traxler (GSI Helmholtzzentrum für Schwerionenforschung GmbH)

Presentation Materials