## ABSTRACT: ##
$~~~$The Gamma-Gamma collider is a scientific facility proposed in China to observe two unique interactions composed of 𝛾𝛾 scattering and electron-positron pairs at the 1-2 MeV cross section. In the experiment, two 𝛾 beams generated by the Compton back-scattering of high-energy electron beams (~$200~$MeV) and high-intensity laser beams collide at the interaction point, and the products are collected by CsI(Na) scintillators and plastic scintillators, and then converted into electric signals by silicon photomultiplier (SiPM) detectors.
$~~~$In this paper, the Front-End Electronics card (FEE) is designed to read out all electric signals from the SiPM detectors, with the feature of high sampling rate and low power consumption. There are 180 differential drivers, 45 low-power switch capacitor array (SCA, DRS4) chips with 8 input channels per chip, 6 ADCs with 8 channels per chip implemented on one FEE. The input signals are firstly stored in DRS4 chips for time stretching, then digitized by ADCs, and finally sent to back-end electronics via an optical link after packaged in an FPGA chip. The noise (RMS) of each readout channel on the FEE version 1 is less than $3~$mV after the offset correction, and the ENOB of the channels is better than $6.7~$bit when the frequency of input signals is less than $70~$MHz. Therefore, the performance of the FEE v1 meets the requirements of the Gamma-Gamma collider.
**1. INTRODUCTION**
$~~~$The Gamma-Gamma collider is under discussion in China proposed by Institute of High Energy Physics (IHEP). The high-energy electron beams (~$200~$MeV) generated by a linear electron accelerator are divided into two arcs, and then brought into a head-on collision at the interaction point (IP). A high-intensity laser beam is illuminated to the electron beams at the conversion points (CP) shortly before they cross the IP, and the process can generate target gamma beams (1-2 MeV) based on Compton back-scattering. Finally, the 𝛾 beams collide at the IP. The planned structure of the 𝛾𝛾 collider facility is shown in Fig. 1.
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Fig.1. A planned structure of the Gamma-Gamma collider facility. |
**2. DESIGN OF THE FRONT-END ELECTRONICS**
*- Readout requirements*
$~~~$In the Gamma-Gamma collider, there are thousands of electric signals to be read out from all SiPM detectors. The detectors are placed in the vaccum cavity to collect the light signals. And technical restrictions of vacuum wall penetration cause the front-end electronics to be placed in the cavity. Due to the compact vacuum area, the front-end electronics requires high integration, which results that each board with the size of 50 cm×25 cm processes 180-channel analog signals from detectors. The power consumption of the front-end electronics is as low as possible to reduce the heat dissipation in vacuum.
$~~~$Based on the selected type of detectors, the pulse width of 𝛾 signals is 2 μs with 600 ns rising edge, the pulse width of electron signals is 30 ns with 10 ns fast rising edge, and the characteristic of positron signals are the superposition of 2 μs slow pulses and 30 ns fast pulses. In order to distinguish the type of particles, the waveform digitizing technology is applied on the readout electronics. Based on the Shannon sampling theory, the analog bandwidth is required better than$~$ 50 MHz. The sampling time window requires to reach at least 2 μs to acquire the whole pulse of particle signals.
$~~~$The target time resolution of detection system is 100 ps (RMS), and the time resolution is composed of the time precision of the detectors and the contribution of the readout electronics. According to the error transfer formula
$N_{whole-system}=\sqrt{N_{detector}^2+N_{electronics}^2}$ $~~~~~~~~~~$ (1)
(N
whole-systemrepresents the time resolution of the detection system, N
detectoris the time precision of the detectors, and N
electronics is the time resolution of the readout electronics), the time resolution of the electronics is required better than 70 ns on the condition that these factors are independent and the resolution of both is equal. Thus the waveform sampling rate needs to be set 1 GSPS based on the time fitting simulation with the same equivalent noise voltage, as shown in Table 1. The noise standard deviation of the readout system is required less than $3~$mV at $1~$V input range. Therefore, it is a good challenge to achieve the design of low noise, high sampling rate and low power consumption.
Table 1. The time resolution of different sampling rate based on the time fitting simulation.
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Sampling rate/GSPS$~~~~$0.2$~~~~~$0.5$~~~~~$1
Time resolution/ps$~~~~$131.6$~~~~$82.5$~~~~$50.8
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*- Basic Structure*
$~~~$A readout electronics system composed of front-end electronics and back-end electronics has been put forward for the Gamma-Gamma collider, as shown in Fig. 2. The front-end electronics is comprised of several Front-End Electronics cards(FEEs) with 180 channels on each board. The back-end electronics is one Data Acquisition board (DAQ).
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Fig.2. Architecture of readout electronics system for the Gamma-Gamma collider. |
*- Design of the FEE*
$~~~$To reach the design of low power consumption, the FEE uses low-power switch capacitor array (SCA) chips and Analog-to-digital converters (ADC) to realize the waveform digitization, as shown in Fig. 3. The SCA chip is called DRS4, each chip consumes around 150 mW at 1 GSPS sampling rate. The working time of the ADCs is controlled by one low-power microsemi Field Programmable Gate Array (FPGA) to reduce the instantaneous power consumption of the FEE. Based on the acceptable quality of the clocks generated by the FPGA, the clock chips are cancelled on the prototype design to decrease the consumption.
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Fig.3. The diagram of the FEE. |
$~~~$There are 180 differential driver (THS4541) circuits on the FEE serving all signals from SiPMs. And 45 DRS4 chips are used to store analog waveforms. One DRS4 chip can deal with 8-channel analog signals and read out the signals at one MUXOUT channel. The sampling time window can reach 2.048 μs when two channels are cascaded inside the DRS4 chip. Then six 12-bit, 40MSPS, serial, ADCs (AD9222) with 8 input channels per chip is applied for waveform digitization. Finally, the FPGA IGLOO2 series is used to record digital data. All the data from the FEE are sent to the DAQ through serial optical links.
$~~~$Fig. 4 shows the photograph of the FEE version 1 (v1), and the board with 8 input channels is used to verify the type selection and performance of the chips.
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Fig.4. The photograph of the FEE v1. |
**3.PERFORMANCE OF THE MESH READOUT CARD**
$~~~$To study the performance of the FEE, the noise and the ENOB were tested in the lab at first. Each sampling cell in the DRS4 chip has a constant offset error, so the calibration waveform is obtained when precision voltage signals generated by an on-board DAC chip were injected into the analog channel. And the noise was sampled with the input floating. After offset correction, the RMS noise of the channels is less than $3~$mV, as shown in Fig. 5.
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Fig.5. Noise waveform of one channel on the FEE v1 after offset correction |
$~~~$The sine signals provided by the SMA100A generator were sent into the FEE through a low-pass filter. By adjusting the frequency of the input pulse with the corresponding filters, the output waveform was sampled. The time interval of 2048 sampling points was calculated at first, then the sine fitting is performed on the time-interval-corrected plots, as shown in Fig. 6. The ENOB of the channels is better than 6.7 bit when the frequency of input signals is less than 70 MHz, based on the formula
$ENOB=log_{2}(\frac{FSR}{NAD(\sqrt{12})}) \approx N-log_{2}(\frac{NAD}{\xi_{Q}})$ $~~~~~~~~$(2)
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Fig.6. One typical sine fitting of the output waveform on the FEE v1. The bule line shows the plots after time-interval correction, and the red line shows the sine fit on the blue plots. |
$~~~$The testing results of the FEE v1 proved the feasibility of the design scheme, and the version 2 of the FEE is in progress to achieve 180-channel readout for the collision experiment.
