from 24 February 2014 to 1 March 2014
Asia/Novosibirsk timezone
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Contribution Oral presentation

Trigger, electronics and DAQ

Performance of the LHCb trigger and its upgrade

Speakers

  • Tim HEAD

Primary authors

Abstract content

The trigger of the LHCb experiment consists of two stages : an initial hardware trigger, and a high-level trigger implemented in a farm of CPUs. It reduces the event rate from an input of 15 MHz to around 5 kHz. To maximize efficiencies and minimize biases, the trigger is designed around inclusive selection algorithms, culminating in a novel boosted decision tree which enables the efficient selection of beauty hadron decays based on a robust partial reconstruction of their decay products. The performance of the LHCb trigger during Run 1 of the LHC is presented. In order to improve performance, the LHCb upgrade aims to significantly increase the rate at which the detector will be read out, and hence shift more of the workload onto the high-level trigger. It is demonstrated that the current high-level trigger architecture will be able to meet this challenge, and the expected efficiencies in several key channels are discussed in context of the LHCb upgrade.