Manuel Dionisio Da Rocha Rolo (INFN)
The design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, carried out at BEPCII in Beijing, is presented. For the upgrade of the inner detector, planned for 2018, a lightweight tracker based on an innovative Gas Electron Multiplier (GEM) cylindrical detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than $130\ \mu$m while loosening the pitch strip to $650\ \mu$m, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates up to 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 100 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s.. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier PCBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This talk will cover the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout, and review the first silicon results of the chip prototype.