Speaker
Mr
Klemens Lautenbach
(JLU Giessen)
Description
The Belle II experiment, at the future SuperKEKB collider in Tsukuba, Japan, features a design luminosity of $8\cdot 10^{35}$ cm$^{-2}$s$^{-1}$, which is a factor of 40 larger than its predecessor KEKB. The pixel detector (PXD) with about 8 million pixels is based on the DEPFET technology and will improve the vertex resolution in beam direction by a factor of 2. With an estimated trigger rate of $30$ kHz, the PXD is expected to generate a data rate of 20 GBytes/s, which is about 10 times larger than the amount of data generated by all other Belle II subdetectors.
Due to the large beam-related background, the PXD needs a data acquisition system with high-bandwidth data links and realtime background reduction by a factor of 10 as otherwise the event builder will be saturated. To achieve this, the Belle II pixel DAQ uses an FPGA-based computing platform with high speed serial links implemented in the ATCA (Advanced Telecommunications Computing Architecture) standard.
The architecture and performance of the data acquisition system and data reduction of the PXD will be presented.
In April 2016 a prototype PXD-DAQ system, which was operated in a test beam campaign, delivered first data with the whole readout chain under realistic, high rate conditions. Final results from the test beam will be presented.
Primary author
Mr
Klemens Lautenbach
(JLU Giessen)
